Ataberk Olgun

Ph.D. Student @ ETH Zurich
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Andreasstrasse 5

8050 Zurich


Ataberk Olgun is a Computer Architecture researcher and a Ph.D. student in SAFARI Research Group at ETH Z√ľrich led by Prof. Onur Mutlu. He obtained his BSc and MSc degrees from TOBB ET√ú under Prof. Ońüuz Ergin‚Äôs supervision.

His research interests lie primarily in the area of Computer Architecture. He is interested in designing reliable (and as performance and energy efficient) memory systems from the ground up. These days, he is trying to develop a better understanding of the RowHammer problem and come up with more efficient system-level solutions to it. Previously, he developed an FPGA-based DDR4 memory testing platform that enabled cutting-edge research characterizing real DDR3/4 and HBM2 DRAM chips. He built an end-to-end system design for processing-in-memory techniques using real off-the-shelf DDR3 chips, which he also prototyped on an FPGA-based system.

He worked at Kasirgalabs until 2021 where he led the design of a RISC-V system-on-chip that was later manufactured using SKY130 technology.

Even before then, he worked with Prof. Kemal Bicakci to develop an authentication method based on behavioral biometrics.

Selected 1st and 2nd Author Publications


    Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture
    Ataberk Olgun, Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, A. Giray Yaglikci, Hasan Hassan, Oguz Ergin, and Onur Mutlu
    ACM TACO, 2024
  2. USENIX Security
    ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation
    Ataberk Olgun, Yahya Can Tugrul, Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah Giray Yaglikci, Geraldo F. Oliveira, and Onur Mutlu
    In USENIX Security, 2024
  3. DSN
    Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
    Ataberk Olgun,¬†Majd Osseiran,¬†Yahya Can Tuńürul,¬†Haocong Luo,¬†Steve Rhyner,¬†Behzad Salami,¬†Juan Gomez Luna,¬†and¬†Onur Mutlu
    In DSN, 2024


  1. ASP-DAC
    Fundamentally Understanding and Solving RowHammer
    Onur Mutlu,¬†Ataberk Olgun,¬†and¬†A Giray YańülńĪkcńĪ
    In ASP-DAC, 2023
    PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
    Ataberk Olgun, Juan Gómez Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, and Onur Mutlu
    ACM TACO, 2023
  3. DSN
    An Experimental Analysis of RowHammer in HBM2 DRAM Chips
    Ataberk Olgun,¬†Majd Osseiran,¬†Yahya Can Tuńürul,¬†Haocong Luo,¬†Steve Rhyner,¬†Behzad Salami,¬†Juan Gomez Luna,¬†and¬†Onur Mutlu
    In DSN Disrupt, 2023
    DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
    Ataberk Olgun,¬†Hasan Hassan,¬†A Giray YańülńĪk√ßńĪ,¬†Yahya Can Tuńürul,¬†Lois Orosa,¬†Haocong Luo,¬†Minesh Patel,¬†Ońüuz Ergin,¬†and¬†Onur Mutlu
    IEEE TCAD, 2023
  5. ISCA
    RowPress: Amplifying Read Disturbance in Modern DRAM Chips
    Haocong Luo,¬†Ataberk Olgun,¬†Abdullah Giray YańülńĪk√ßńĪ,¬†Yahya Can Tuńürul,¬†Steve Rhyner,¬†Meryem Banu Cavlak,¬†Jo√ęl Lindegger,¬†Mohammad Sadrosadati,¬†and¬†Onur Mutlu
    In ISCA, 2023


    MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations
    Nandita Vijaykumar, Ataberk Olgun, Konstantinos Kanellopoulos, F Nisa Bostanci, Hasan Hassan, Mehrshad Lotfi, Phillip B Gibbons, and Onur Mutlu
    ACM TACO, 2022


  1. ISCA
    QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
    Ataberk Olgun,¬†Minesh Patel,¬†A Giray YańülńĪk√ßńĪ,¬†Haocong Luo,¬†Jeremie S Kim,¬†F Nisa BostancńĪ,¬†Nandita Vijaykumar,¬†Ońüuz Ergin,¬†and¬†Onur Mutlu
    In ISCA, 2021